1. Field of the Invention
This invention relates to clock tree synthesis (CTS) methods, and more particularly, to a gated CTS method which can help make the design of a gate array logic circuit less complex and less difficult for the designer, and which can make the resultant logic circuit more efficient in clocking performance.
2. Description of Related Art
In the manufacture of logic circuits, a common practice is the utilization of the so-called ASIC (application-specific integrated circuit) technology. ASIC technology involves fabrication of a special type of chip as a nonspecific collection of logic gates, and later in the manufacturing process, addition of a layer connecting the gates so as to provide the specified logic function. Where efficient power management is desired, the conventional gated CTS methods can be utilized to reduce power consumption. In these methods, the clock signal to a certain logic element will be enabled only when the logic element is in active operation; otherwise, the clock signal will be disabled. As a result, the power consumption of the logic element can be reduced. One drawback of the conventional CTS methods, however, is that they can be used only to synthesize on gated buffer, and is unable to synthesize gated clock buffer. Due to this drawback, the required logic gates in a buffer need to be additionally provided by the designer, which makes the design very complex and difficult for the designer. Besides, the transmission of the clock signals from one point to another can suffer from distortions due to lengthy transmission paths in cases where a gated clock signal is used to drive latches or registers, since a single buffer can be used for the transfer of various gated clock signals or non-gated clock signals.
FIG. 1 is a schematic diagram of a first example of a logic circuit, which is synthesized by utilizing a conventional gated CTS method. As shown, the logic circuit includes a clock generator 10, a plurality of buffers 11, 12, a plurality of AND gates 13, 14, 15, and a plurality of flip-flops 16, 17, 18, 19. The clock generator 10 is used to generate a clock signal which is buffered by the buffers 11, 12 and then gated by the AND gates 13, 14, 15 under control of the control signals A, B to be subsequently used to clock the flip-flops 16, 17, 18, 19. The outputs from the AND gates 13, 14, 15 respectively (for example the output CLK1 from the AND gate 13) are each referred to as a gated clock signal, whereas the clock signal CLK2 that is directly used to clock the flip-flops 16, 17 is referred as a non-gated clock signal.
FIG. 2 is a schematic diagram of a layout example, which is synthesized by conventional CTS method. As shown, this logic circuit includes a clock generator 20, a plurality of buffers 21, 22, a plurality of AND gates 23, 24, and a plurality of flip-flops 25, 26, 27. The buffers 21, 22 are used to transfer the output clock signal from the clock generator 20, and subsequently the outputs of the buffers 21, 22 are respectively used directly to drive the flip-flops 25, 26, 27. Meanwhile, the outputs of the buffers 21, 22 are respectively gated by the AND gates 23, 24 under control of the control signal C. The gated clock signal from the AND gate 23 is then used to drive the logic elements 31, 32 while the gated clock signal from the AND gate 24 is used to clock the next-stage logic element 33.
One drawback to the foregoing logic circuits, however, is that they may fail to provide optimal localization of the logic elements in the gate array such that the signal transmission can suffer from an increased time delay that degrades the performance of the circuit. In the case of FIG. 1, for example, those logic elements whose clock signals are enabled by the control signal A are arranged in separate areas. In the case of FIG. 2, for example, the gate control signal C needs to jump over the line between the output of the buffer 21 and one input of the AND gate 23 and then extend a long ways to the AND gate 24. The time delay in the control signal transferred over the lengthy line can thus be large, which degrades the performance of the logic circuit. There exists, therefore, a need for a new gated CTS method that represents a solution to this problem.